| 摘要 |
<p>A method and an apparatus utilizing mux scan flip-flops (62, 68, 75, 81 and 87) to test for timing-related defects. In one embodiment, a delay circuit (54) is used to act as a buffer for a scan enable signal received by the mux scan flip-flops (62, 68, 75, 81 and 87) of a test circuit. The scan mode signal is first sent to delay circuit (54), which then distributes the scan mode signal to the mux scan flip-flops (62, 68, 75, 81 and 87). Since each delay circuit (54) can serve as the buffer for numerous mux scan flip-flops (62, 68, 75, 81 and 87). The scan mode signal may be sent initially to a smaller number of delay circuits (54) instead of the thousands of mux scan flip-flops (62, 68, 75, 81 and 87) that may be distributed throughout the entire intergrated circuit. Furthermore, in one embodiment the delay circuit delays propagation of active-to-inactive transition of the scan enable signal by one clock cycle, synchronizing the system clock cycle with the active-to-inactive transitions of the scan enable signal are propagated without the one clock cycle delay. With the present invention, the mux scan flip-flops (62, 68, 75, 81 and 87) may be loaded and unloaded with test data at slower clock speeds.</p> |
