REDUCED CAPACITANCE TRANSISTOR WITH ELECTRO-STATIC DISCHARGE PROTECTION STRUCTURE AND METHOD FOR FORMING THE SAME

摘要

A method and apparatus is disclosed for providing a reduced capacitance transistor with ESD protection that can be fabricated using standard processes. The transistor includes a substrate (310), a source (340) region formed in the substrate, and a well region also formed in the substrate. The transistor further includes a drain (315) region having a first end region, a second region, and a resistive region positioned between the first and second end regions. The drain region is formed at least partially in the well region. A drain contact is formed on the first end region of the drain region. The gate structure (330) is formed on the substrate between the source region and the second end region of the drain region. The gate structure defines a channel region that couples the source region to the drain region.