Synchronous dynamic random access memory architecture for sequential burst mode

摘要

An electronic memory device which includes a memory array having a plurality of memory cells arranged into a plurality of units. Each unit is divided into a first portion including only even addressed memory cells and a second portion including only odd addressed memory cells. A column decoder and row decoder are coupled to the memory array for selecting a number of the plurality of memory cells. A sense amplifier is coupled to the memory array for performing read and write operations from the selected memory cells. An address line is split for application of a split address to said even and odd addressed memory cells.