BUFFER CIRCUIT AND INTEGRATED-CIRCUIT MEMORY WITH A BUFFER CIRCUIT

摘要

The invention relates to a buffer circuit for buffering a supply voltage (U) of an integrated circuit, said supply voltage being connected between two potential nodes (1, 2). Said buffer circuit has a series-parallel circuit which consists of a buffer capacitor (C) and a high-impedance resistance element (R; TN; TP), and which is located between the two potential nodes (1, 2). The high-impedance resistance element limits the current in the event of a fault in the buffer capacitor (C).