发明名称 MPEG data stream decoder
摘要 A synchronous control method for a coded signal decoding circuit is disclosed for processing a bit stream consisting of a plurality of successive frames each including sample data of a coded signal to be decoded, and header information having synchronous information indicating a starting position of a frame as a unit of processing and information indicating the frame as a first kind of frame consisting of a relatively small number of sample data per frame or a second kind of frame consisting of a relatively large number of sample data per frame, comprising the steps of: extracting the header information from each frame in said bit stream; detecting whether the state is a synchronized state or an asynchronous state on the basis of the synchronous information included in the extracted header information; judging whether the frame is said first kind or said second kind on the basis of the extracted header information; and performing synchronous control, based on the judgement result on the kind of frame, the synchronous detection result, and the current state, by judging at least whether the next state is a first state indicating an initial state or indicating that the synchronized state has not been detected, a second state indicating that the synchronized state has been detected, a third state indicating that the synchronized state has not been detected in said second state when the contents of said header information indicates the frame is said first kind, or a fourth state indicating that the synchronized state has not been detected in said second state when the contents of said header information indicates the frame is said second kind. <IMAGE>
申请公布号 EP0786908(A3) 申请公布日期 1999.06.23
申请号 EP19960305599 申请日期 1996.07.29
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 HIRAKI, TOSHIYUKI;YAMADA, AKIRA;OKI, MASASHI
分类号 H03M7/30;H04B14/04;H04L7/10;H04N7/169;H04N7/171;H04N7/24;H04N7/50;H04N7/52;H04N21/2368;H04N21/43;H04N21/434 主分类号 H03M7/30
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