Multiple clock frequency divider with fifty percent duty cycle output

摘要

A clock divider circuit and a system using the same. The clock divider circuit has a clock input coupled to receive an input clock signal having an input clock frequency. Clock division logic generates an output clock signal having a fifty percent duty cycle and an output clock frequency which is an odd fraction of the input clock frequency. The clock division logic generates both the rising and the falling clock edges of the output clock signal from the input clock signal. The system disclosed includes a processor operating at a first frequency and a memory circuit coupled to exchange data with the processor. The processor includes a clock division circuit coupled to receive a first clock signal and to generate a second clock signal at a second frequency which is an odd fraction of the first frequency. The processor also includes an input/output buffer coupled to exchange data with the memory circuit. The memory circuit is coupled to receive the second clock signal to synchronize transmission of data between the processor and the memory circuit.