Cross clock domain clocking for a system using two clock frequencies where one frequency is fractional multiple of the other

摘要

A processor includes a processing core that is operable at a frequency that is an odd half-integer multiple of a bus clock frequency. Signals on a system bus are synchronized with a selected edge, e.g., the rising edge, of a bus clock signal, but the processing core requires signals synchronized with a processor clock signal. Signal crossing between the clock domain of the processing core and the clock domain of the system bus pass through a storage element that selectably latches a value of the signal either at a rising edge or a falling edge of the processor clock signal. A control circuit selects either rising-edge or falling-edge latching depending on which edge (rising or falling) is closest to being synchronized with the selected edge of the bus clock signal.