| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce a circuit scale in the case of delaying only the rise or fall of signals as one element of a logic circuit and to prevent an abnormal operation. SOLUTION: This delay circuit for inputting required logic input signals and obtaining target delay signals for which the signals are delayed is constituted of an inverter circuit 2 for outputting inverted signals Sr for which the input signals Sin are inverted and the (n) pieces (n) is an integer >=1} of small-sized delay circuits 31-3n. The small-sized delay circuits 31-3n are provided with three input terminals and one output terminal, the input signals Sin are inputted to a first input terminal, the input signals or the output of the small- sized delay circuit of a preceding stage are inputted to a second input terminal, the inverted signals Sr of the inversion circuit 2 are inputted to a third input terminal and the target delay signals are obtained from the output terminal Sout. By turning the output of the small-sized delay circuit 3n of a final stage to the delay signals, output signals for which only the rise is delayed are obtained.</p> |
