| 摘要 |
A semiconductor memory device resets a latch data output before new data is transferred in a successive data output mode, in order to improve a high-speed access operation of the semiconductor memory. Data stored in a memory cell of a memory cell array or a register portion arranged in a column direction are successively accessed with a signal /CAS as a trigger. The accessed data is output through an output buffer in a clock cycle between a trigger of the signal /CAS and a next trigger thereof. In the output buffer of the semiconductor memory, immediately before an output cycle of new data transmitted from the memory cell through a data line, the previous data is reset and a data output portion is set to a high-impedance state by the signal /CAS. Thereafter, the new data is supplied to the output buffer through the data line.
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