| 摘要 |
PROBLEM TO BE SOLVED: To increase read/write operation speed of data for a memory cell by reducing a load of a bit line. SOLUTION: This device has a memory cell 11 connected to a bit line B1 and selected by a word line W1, a memory cell 12 connected to a bit line B2 and selected by a word line W2, a N type transistor 13 for pre-charging the bit line B1 to a first potential level, a P type transistor 14 for pre-charging the bit line B2 to a second potential level being lower than the first potential level, and a sense amplifier circuit 15 outputting 0 in a state in which a potential level of the bit line B2 is lower than the first potential level, and amplifying a potential difference between the bit lines and outputting it when a potential level of the bit line B2 is raised and exceeds the first potential level or a potential level of the bit line B1 is dropped and is less than the second potential level. |
