CLOCK SIGNAL REPRODUCING DEVICE

摘要

PROBLEM TO BE SOLVED: To reduce the operating speed of an A/D converter and the oscillation frequency of an oscillator into 1/2 conventional frequency. SOLUTION: An A/D converter B samples a demodulate data signal 110 from an input terminal 14 synchronously with a clock signal 12 and converts it to a digital signal 9. Then, an oscillator control circuit 10 supplies a controlled voltage corresponding to the level of the digital signal 9 outputted by the ADD converter 8 to an oscillator 4 and based on a change direction signal 7 outputted by a signal change direction detecting circuit, it is switched whether a controlled voltage 5 is to be increased with the increase of the digital signal 9 or to be inversely decreased. As a result, a clock signal 12 generated by the oscillator 4 makes its frequency correspondent to the bit rate of the demodulate data signal 110 and fixes its phase to the demodulate data signal 110, and this signal is outputted from an output terminal 122 as a clock signal reproduced from the demodulate data signal 110.