| 摘要 |
<p>PROBLEM TO BE SOLVED: To evaluate a test for improving reliability at a developing time while removing an effect of a genuine defect bit by providing a read-out test mode selectively charging a bit line of a column to be read out based on the data latched with a sense latch circuit, reading out the cell data of a memory cell and detecting bit line potential. SOLUTION: A sense amplifier consists of transistor M1-M7 and the latch circuit LT, and charges only the bit line connected to the cell to be read out among a bit line group according to the latch data of the latch circuit LT at the time of read-out at a read-out test time. In such a case, the latch data are written in beforehand by the data different according to the column to be read out/not to be read out. Thus, by making the column that the genuine defect bit exists the column not to be read out, the read-out test is executed in the state removing the genuine defect bit.</p> |
