发明名称 Computer architecture for the deferral of exceptions on speculative instructions
摘要 The inventive system and method allows for software control of hardware deferral of exceptions in speculative operations, and comprises three components. The first component is processor stored information which reflects the code generation strategy of applications and is used by hardware and the operating system to control exception deferral. The second component is processor stored information set by the operating system to specify to hardware which type of faults should be automatically deferred. The third component is further processor stored information which indicates to the hardware to defer certain exception causing aspects of the speculative operation, while performing other non excepting aspects of the speculative operation. The stored information is set after the operating system exception handler has unsuccessfully attempted fault resolution.
申请公布号 US5915117(A) 申请公布日期 1999.06.22
申请号 US19970949295 申请日期 1997.10.13
申请人 INSTITUTE FOR THE DEVELOPMENT OF EMERGING ARCHITECTURES, L.L.C. 发明人 ROSS, JONATHAN K.;MILLS, JACK D.;HAYS, JAMES O.;BURGER, STEPHEN G.;MORRIS, DALE C.;THOMPSON, CAROL L.;GUPTA, RAJIV;FREUDENBERGER, STEFAN M.;HAMMOND, GARY N.;KLING, RALPH M.
分类号 G06F9/38;(IPC1-7):G06F9/38 主分类号 G06F9/38
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