| 摘要 |
PROBLEM TO BE SOLVED: To provide a digital PLL circuit and a signal reproducing method with which pull-in time can be shortened while efficiently utilizing a data area without lowering durability to the jitter fluctuation or duty distortion of an input data signal. SOLUTION: This circuit has a data sampling processing part 1 for sampling the input data signal and outputting N pieces of sample data signals, data reproducing processing part 3 for outputting a regenerative data signal based on the sample data signal 6 outputted from the data sampling processing part 1 and an N-phase clock signal and delay processing part 2 for delaying the inputted sample data signals 6 and outputting them to the data reproducing processing part 3 as delay sample data signals 7, and time to the selective output of the extracted clock signal based on the phase information of the input data signal is shortened rather than time to the output of the input data signal as the regenerative data signal. |
