| 摘要 |
A digital demodulator capable of a high speed operation. An automatic frequency controller (AFC) estimates a frequency deviation DELTA omega on the basis of a detected sample signal which is outputted at an oversampling interval by a receiving filter. The AFC can estimate the frequency deviation before a stable operation of a bit timing recovery circuit (BTR). The AFC generates a frequency deviation correcting signal for each decision timing on the basis of the estimated frequency deviation, and decision timing information from the BTR. A multiplier eliminates a frequency deviation component from an input signal in response to the frequency deviation correcting signal.
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