发明名称 |
METHOD AND SYSTEM FOR SINGLE CYCLE DISPATCH OF MULTIPLE INSTRUCTIONS IN A SUPERSCALAR PROCESSOR SYSTEM |
摘要 |
A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units for execution and placement of results thereof within specified general purpose registers. Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers are provided and each time an instruction is dispatched to an available execution unit, a particular one of the intermediate storage buffers is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register or a designated alternate general purpose register. |
申请公布号 |
CA2107304(C) |
申请公布日期 |
1999.06.22 |
申请号 |
CA19932107304 |
申请日期 |
1993.09.29 |
申请人 |
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发明人 |
KAHLE, JAMES ALLAN;KAU, CHIN-CHENG;LEVITAN, DAVID STEVEN;OGDEN, AUBREY DEENE;POURSEPANJ, ALI ASGHAR;TU, PAUL KANG-GUO;WALDECKER, DONALD EMIL |
分类号 |
G06F9/38;(IPC1-7):G06F15/16 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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