FAIL-SAFE TIMER CIRCUIT AND ON-DELAY CIRCUIT USING THE SAME

摘要

A fail-safe timer circuit which does not generate such an erroneous output that shortens delay time when a fault occurs and an on-delay circuit. The timer circuit comprises an oscillator circuit (11) which generates a timer output from the cathode terminal of a PUT prescribed period after an input signal (VIN) is received and a monitoring circuit (12) which monitors the operation of the oscillator circuit (11). The on-delay circuit comprises a latch (13) which has a first terminal (a) for receiving the input signal (VIN) and a second terminal (b) for receiving an output signal (Vo) that the monitoring circuit produces only when it is confirmed that the oscillator circuit (11) is normal by detecting a fall of a cathode terminal voltage of the circuit (11). The latch generates an output signal only when both the input signals are higher in level than the power supply potential, and maintains the state.