| 摘要 |
<p>PROBLEM TO BE SOLVED: To suppress increase in chip area to minimum, to allow built-in circuit, and to provide efficient failure detection, by providing a PAD for test circuit on a semiconductor chip isolation region. SOLUTION: On an isolation region 2 isolating semiconductor chip 1 formed in plural numbers on a semiconductor wafer, a signal input pad 4 for operation/ non-operation control of a test circuit built in the semiconductor chip 1 is provided. The pad 4 is connected to an adjoining semiconductor chip internal test circuit through a wiring layer 9. After the semiconductor chips 1 are cut along the isolation region 2, the wiring layer 9 is pulled down to a VSS at high resistance for non-test mode. After completion of test on the wafer, dicing is performed along the isolation region 2, so that a test pad on the isolation region 2 disappears. For use as a product thereafter, since a test signal input line is connected to a ground terminal at high resistance, non-test mode is obtained at all times.</p> |
