| 摘要 |
<p>PROBLEM TO BE SOLVED: To minimize the delay between a clock signal on a bus line and output data to be outputted outside. SOLUTION: An F/F 104n is supplied with a clock signal A supplied from the bus line 101 as a clock signal B which is only distributed by a distributor 102 and does not have its frequency divided, and a clock signal C after having its frequency divided by a frequency divider 103 is supplied as a hold signal. Even when the clock signal B before frequency division is inputted, holding is done with the frequency-divided clock signal C, so the same operation is performed. Then the delay of the output signal is reduced as compared with an F/F 1061 using the frequency-divided clock signal C as its clock.</p> |
