| 摘要 |
<p>PROBLEM TO BE SOLVED: To enable micronization and high integration of an element, improve isolation capability and reduce parasitic resistance, parasitic capacity, etc., a well by arranging an NAND string formed of a plurality of memory cell transistors with are connected in series mutually a matrix in a memory cell array. SOLUTION: A silicon thin film 12 is formed on an insulation layer 11 formed on a substrate 10. An insulation material is put between lattice-like silicon thin films 12 which function as element isolation. Each memory cell transistor is constituted of an n-type diffused layer 18, a floating gate electrode 15 formed on a channel region between the n-type diffused layers 18 via a gate oxide film 14 in between and a control gate electrode 17 formed on the floating gate electrode 15 via an insulation film 16 in between. Each selective gate transistor is constituted of n-type diffused layers 18, 18-S, 18-D and gate electrodes SGS, SGD formed on a channel between the n-type diffused layers 18, 18-S, 18-D with a gate oxide film 14A inbetween.</p> |
