| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a programmable delay line capable of ensing a cycle or a half cycle of an input clock accurately and at a high speed irrespective of the operating voltage, the temperature, the step change, etc. SOLUTION: This programmable delay line comprises a delay line 101 which is constituted by a plurality of unit delayers connected in series, and in which is clock PCLK in is a input; a phase comparison part 103 for comparing the phase of an output of each unit delayer with the phase of the clock PCLKin; and a switching part 105 for selecting any one of outputs of each unit delayer in response to control bits p1 to Pn and outputting the selected one. This programmable delay line further comprises a pointer 107 for generating th control bits P1 to Pn; and a control part 109 for performing control so as to initialize the pointer 107 when an output of the phase comparison part 103 is equal to the control bits P1 to Pn and an up instruction UP is applied, and performing control so as to load an output of the phase comparison part 103 to the pointer 107 when the pointer 107 is initialized and a down instruction DOWN is applied.</p> |
