FIXED WIRELESS LOOP SYSTEM HAVING DUAL DIRECT SYNTHESIZER

摘要

Disclosed is apparatus including circuitry for providing synchronizing clocks to a transmitter and a receiver of a subscriber unit (SU, 14) that communicates with a radio base unit (RBU, 12) in a synchronous CDMA communication system. The apparatus includes an accumulator (17B) for generating a digital signal having a changing magnitude. The accumulator (17B) is initialized to a value of a phase command received from the RBU (12). The apparatus further includes a first circuit for converting a content of the accumulator (17B) to a synchronized receiver clock signal. The apparatus further includes a summer circuit for combining the content of the accumulator (17B), representing the commanded receiver side phase difference from RBU timing, with a value of a transmitter timing offset commanded by the RBU (12). The summer circuit provides a summation signal to a second circuit that converts the summation signal to a synchronized transmitter clock signal.