| 摘要 |
<p>Shadow registers for processing interruption are provided in a CPU. When the control shifts to interruption routine, the shadow registers are used for the interruption routine by changing the use of ordinary registers thereto, and the ordinary registers are prohibited to be used during a period of the interruption. Subsequently to the finish of the interruption, the ordinary registers are re-used without the necessity of the store and the re-store of the ordinary registers. <IMAGE></p> |
