发明名称 Semiconductor device having a multi-layered wire structure
摘要 After forming a first wire on a first interlayer insulation film, a second interlayer insulation film is formed and planarized, to thereby form a via hole. At this stage, the via hole is formed off the first wire. Next, after making an exposed edge and an exposed side wall of the first wire slanted surfaces, a second wire is formed with or without a conductive film buried within the via hole. Since the side wall of the first wire is a slanted surface in this manner, it is possible to completely bury a wire material of the second wire or the conductive film within the via hole, and therefore, it is possible to ensure electric conduction all over the slanted surfaces of the first wire. As a result, even if the via hole which connects the first wire in a lower layer and the second wire in an upper layer is formed off the first wire, an increase in a wire resistance in the via hole is prevented. <IMAGE>
申请公布号 EP0788160(A3) 申请公布日期 1999.06.16
申请号 EP19970101733 申请日期 1997.02.04
申请人 MATSUSHITA ELECTRONICS CORPORATION 发明人 NISHIMURA, HIROSHI;OGAWA, SHINICHI
分类号 C23F4/00;H01L21/28;H01L21/302;H01L21/3065;H01L21/768;H01L23/522;H01L23/532 主分类号 C23F4/00
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