| 摘要 |
A method of mfg. a memory cell structure comprises providing a cell having trench isolation and active regions, the latter being covered with gate silica and poly-Si, depositing a thin insulator and etching with a mask to expose the gate poly-Si. A gate conductor and cap are deposited and these and the gate poly-Si stopping etched as above. Spacers, junctions, passivation, contacts and wiring are then added. The cell is provided by depositing silica, gate poly and a pad on the cell, deep trench processing, etching using a shallow trench isolation mask and depositing silica fill and planarising. Gate silica and poly-Si are planarised to the same height as the silica fill. |
