| 摘要 |
At least one slit (4a, 4b) having a predetermined shape is formed around a contact region of a lower wiring layer (1) formed on a substrate (5), and insulating portions (6a, 6b) formed integrally with an insulating layer (6) is embedded in these slits (4a, 4b). This insulating layer (6) is formed on the lower wiring layer (1) and has a contact hole (3) located at a position corresponding to the contact region. Since the insulating portions (6a, 6b) as a wedge-like portion project into the slits downwardly from the rigid insulating layer (6), positional errors caused by thermal expansion of the lower wiring layer (1) in annealing of the upper wiring layer (2) can be suppressed, and an abnormal geometry such as a projection on the upper wiring layer (2) can be prevented. In addition, a semiconductor device free from interwiring short-circuiting and excellent in flatness can be obtained. |
