Method and apparatus for synchronization word detection

摘要

A communication system (10) comprising circuitry (RCVR1) for receiving a bitstream packet (P). The bitstream packet comprises at least three groups of bits: (i) a plurality of preamble prefix bits having a predetermined bit pattern; (ii) a plurality of synchronization word bits following the plurality of preamble prefix bits; and (iii) a plurality of data bits following the plurality of synchronization word bits. The system further includes circuitry for completing a carrier and clock recovery operation in response to receiving a first portion of the plurality of preamble prefix bits. Still further, the system includes circuitry (30) for determining a location of the plurality of synchronization word bits within the bitstream packet. The circuitry for determining comprises circuitry (36) for performing a number of comparisons between a bit test pattern vector (32) and a sample vector (34) of bits from the bitstream packet. The bit test pattern vector and the sample vector of bits both change for each of the number of comparisons. For at least one of the number of comparisons the sample vector of bits comprises a second portion of the plurality of preamble prefix bits following the first portion of the plurality of preamble prefix bits. Further, for at least some of the number of comparisons, the bit test pattern vector comprises one or more bits matching the predetermined bit pattern of the plurality of preamble prefix bits and further comprises one or more bits matching the synchronization word bits. <IMAGE>