| 摘要 |
A VRAM-based parity engine for use in a disk array controller is disclosed, in which the parity arithmetic operation is carried out in a fast and effective manner, thereby improving the performance of the RAID system. Particularly, the parity data arithmetic operation is not resorted to a processor, but to a VRAM, thereby realizing a high speed operation. In the disk array controller, a VRAM (video RAM) is used, in such a manner that the reading, updating and writing are made to be overlapped during the arithmetic operation, thereby promoting the speed of the arithmetic. Therefore, a relatively large capacity memory can be formed compared with the conventional SRAM, and therefore, a temporary buffer memory within the parity engine is used as a parity cache, thereby doubling the performance. |
