| 摘要 |
A microprocessor (10) and system (2) including a multi-stream pipeline unit (25) are disclosed. The multi-stream pipeline unit (25) includes individual fetch units (26), instruction caches (16i), and decoders (34) in separate instruction streams (PROC0, PROC1) or pipelines. A common scheduler (36) is provided to check for dependencies among the instructions from the multiple instruction streams (PROC0, PROC1), and to launch instructions for execution by the various execution units (31, 40, 42, 50), including a microcode unit (47). A common register file (39) includes register banks (70) dedicated to each pipeline, and also a register bank (72) that includes temporary and shared registers available to instructions of either instruction stream (PROC0, PROC1), such as useful in the event of register renaming due to a dependency. Each decoded instruction in the scheduler (36) has an identifier (PROC) indicating the one of the instruction streams (PROC0, PROC1) from which it was issued. In the event of an exception requiring one of the pipelines to be flushed, the decoded instructions in the scheduler (36) associated with the flushed pipeline may be invalidated (i.e., the results of their execution ignored), while the instructions in the scheduler (36) associated with the other pipeline may continue to advance and execute normally.
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