发明名称 |
MOSFET having buried shield plate for reduced gate/drain capacitance |
摘要 |
Gate to drain capacitance in a lateral DMOS and vertical DMOS field effect transistor is minimized by providing a conductive shield plate under the gate and between the gate and the drain of the transistor. In operation, the shield plate is preferably connected to a DC voltage potential and coupled to AC ground for RF power applications. The shield plate is readily fabricated in a conventional polysilicon gate process by adding one additional polysilicon deposition (or other suitable material), one additional mask, and one additional etch step. The shield plate can include a raised portion which provides lateral capacitive isolation between the gate and the drain. Alternatively, a shield contact can be provided above the shield plate and between the gate and drain to provide lateral isolation.
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申请公布号 |
US5912490(A) |
申请公布日期 |
1999.06.15 |
申请号 |
US19970905513 |
申请日期 |
1997.08.04 |
申请人 |
SPECTRIAN |
发明人 |
HEBERT, FRANCOIS;NG, DANIEL |
分类号 |
H01L23/552;H01L27/088;H01L29/06;H01L29/40;H01L29/78;(IPC1-7):H01L29/72 |
主分类号 |
H01L23/552 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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