| 摘要 |
A power up pulse generator circuit generates a pulse of predetermined duration in spite of a slow rate of change of applied power supply voltage. The circuit has application to integrated logic circuits that begin operation from an initial condition after the application of the power supply voltage and an input signal. In one embodiment, a dynamic random access memory (DRAM) of the present invention begins operation after receiving an address strobe signal. The address strobe signal is coupled to the power up pulse generator circuit to assure that the power up pulse is of sufficient duration to reset internal registers and so establish the initial condition. The power up pulse generator circuit of such an embodiment includes a selectively enabled input buffer, a selectively enabled one shot, and a flip flop designed to assume a predetermined state on application of the power supply voltage.
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