| 摘要 |
In order to modify a combination of logic gates based on relationships between physical locations of the logic gates in a semiconductor integrated circuit which has already been subjected to layout design in the middle of design of the semiconductor integrated circuit, circuit portions whose combination is to be modified are specified, then the circuit portions are transformed into logically equivalent intermediate representations (NAND2s, IVs, etc.), then anew combination of the logic gates is generated based on the intermediate representation, and then the prior combination of the logic gates is replaced with the new combination of the logic gates.
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