| 摘要 |
A method and apparatus are presented for operating a time slicing shared memory swith (300). The apparatus (300) includes a bus for receiving a plurality of data frames (11) in a respective plurality of input channels to the switch. A slice crosspoint applies the plurality of data frames to a shared memory (330) in a time sliced manner. The time slice is established for each section of a shared memory to be staggered so that on any clock cycle, one memory portion is being accessed for writing (524, 526, 528, 530) at least some of the data frames and on a next clock cycle the memory portion is accessed for reading (537, 538, 539, 540) at least a portion of the data.
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