发明名称 CLOCK SIGNAL GENERATING CIRCUIT OUTPUTTING PLURAL CLOCK SIGNALS WITH DIFFERENT PHASE AND CLOCK PHASE CONTROL CIRCUIT USING THE SAME
摘要 PROBLEM TO BE SOLVED: To obtain a clock signal generating circuit that is manufactured by a CMOS process and suitable for controlling a light-emitting element, such as a laser diode. SOLUTION: This generating circuit has a preliminary phase change circuit 9 that generates plural preliminary delay clock signals phase of which differ from each other, based on an input clock signal and a main phase change circuit 10 that receives the plural preliminary delay clock signals to generate plural main delay clock signals or each preliminary delay clock signal, so as to provide an output of algae number of amin delayed clock signals.
申请公布号 JPH11150456(A) 申请公布日期 1999.06.02
申请号 JP19970314008 申请日期 1997.11.14
申请人 MITSUBISHI ELECTRIC CORP 发明人 SUGA YASUHIRO;TANIGUCHI MASAHARU
分类号 H03K5/13;H03K5/135;H03K5/15;H03L7/07;H03L7/081;H03L7/093 主分类号 H03K5/13
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