Huffman code decoding circuit

摘要

A huffman code decoding circuit has a memory (10) storing a decoded word and a code length or a pointer to be accessed in the next time determined on the basis of a state transition upon decoding of a bit variable length code per every one or n bits and a flag representative of the decoding condition of the code and outputting the decoded word and the code length or the pointer for next access and the flag corresponding to an access address of m bits. A latching circuit (11) latches the pointer of m-1 bit output from the memory (10) when the flag is indicative of continuation of decoding, and is reset when the flag output from the memory (10) is indicative of completion of decoding. A selector (12) selectively outputs n-1 bit from one of the latching circuit (11) and the bit variable length code to the memory (10), according to selection for decoding of the bit variable length code per every 1 bit or every n bit. <IMAGE>