| 摘要 |
PROBLEM TO BE SOLVED: To obtain a PLL(phase locked loop) circuit, in which wide capture and wide locking are carried out even by simple constitution. SOLUTION: In a wide mode, wide capture is attained by inputting error information between an output from an FCO(frequency, comparator output) counter 45 and the measured value (EFM (8-14 modulation) frequency) of a CLV(constant linear velocity) speed counter 33 as the error control signal of a VCO(voltage controlled oscillation circuit) 44 through an integrating circuit 48, a D/A converter 49 and an adder 43 at the time of servo leading-in. An input to the integrating circuit 38 is changed over to the phase-error low-pass component of a PLCK by a PCI (phase comparator integration) circuit 50 and an EFM signal under the state, in which a PLL circuit is locked. Accordingly, the oscillation frequency of the VCO is operated so as to be followed up to EFM signal frequency corresponding to disk rotational speed, and a lock range is widened. The PCI circuit 50 is constituted so as to conduct counting at a level obtained by sampling the PLCK at EFM edge timing. |
