| 摘要 |
PROBLEM TO BE SOLVED: To eliminate a phase difference between complementary signals outputted from a register circuit. SOLUTION: A single line type constitutes a master side latch circuit of a register and a double type constitutes a slave side latch circuit. A first latch circuit consists of transfer gates TG11, TG12 of series connection which are controlled by a clock signal and inverse of the clock signal and of inverters INV11, 12 forming a flip-flop, and a second latch circuit consists of transfer gates TG13, TG15, 14, 16 of series connection controlled by a clock signal and inverse of the clock signal and of inverters INV13, 15 that receive signals from the transfer gates TG13, TG15, 14, 16 and provide an output of complementary signals. Thus, the phase difference of the outputted complementary signals is eliminated, while minimizing the increase in number of components. |
