| 摘要 |
PROBLEM TO BE SOLVED: To obtain a PLL synchronization system by shortening time until an output of a PLL is made stable, when any of plural systems of clocks is switched over and a desired system is selected. SOLUTION: A PLL circuit, consisting of a phase comparator 2, an LPF 3, a DC amplifier 4, a loop filter 8 and VCO 9, is used to prepare changeover of clock systems. Plural phase comparators 2, LPFs 3, and DC amplifiers 4 are prepared, a differential amplifier 6 detects clock phases prior to changeover, and the phase having been detected at changeover of the clock systems is fed to the VCO 9 through a loop filter by closing a switch SW 5. The loop gain is instantaneously increased by the phase difference of a received clock. Thereafter, when an output phase of the PLL is close to the phase of the selected clock, an output of the differential amplifier becomes smaller and the switch is open, when the output reaches a prescribed level or below. |
