Integrated CMOS circuit, e.g. for DRAM, logic

摘要

The CMOS circuit has a substrate (1) with monocrystalline silicon adjacent at least one surface, covered by a dielectric layer (2), with an insulation structure (6) adjacent the surface, for relative insulation of neighbouring MOS transistors having oppositely doped gate electrodes. The lower part (12,16) of at least one of the latter gate electrodes is partially enclosed by the insulation structure, with a diffusion barrier (19) within the gate electrode, the upper part (17) of which is coupled to the gate electrode of at least one further MOS transistor.