| 摘要 |
PROBLEM TO BE SOLVED: To suppress the effect of noise between adjacent bit lines at the time of rewriting by recording the first transfer gate region for separating the sub-bit lines for multilevel writing into two at the center thereof, a plurality of second transfer gates for activating one of a plurality of sub-bit lines selectively, and the order of every other pair of complementary sub-bit lines is interchanged. SOLUTION: The order of every other pair of complementary sub-bit lines (BLT03 and BLN03, and the like) is interchanged in the element region of transfer gates using the diffused layer part of the transfer gates by means of the first transfer gates 12 for multilevel writing which separate a plurality of sub-bit lines into two at the center in a multilevel dynamic semiconductor memory voice where four potential levels are written in one memory cell. Consequently, noise due to capacitance between adjacent bit lines is reduced and the operational margin is enhanced in a structure where a plurality of sub-bit lines sharing a single sub-sense amplifier SSA operate in time division mode. |
