Apparatus for sampling multiple concurrent instructions in a processor pipeline

摘要

An apparatus is provided for sampling multiple concurrently executing instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. When the instructions are fetched into a first stage of the pipeline, the apparatus identifies multiple selected instructions as a subset of the instructions that one executed concurrently in the pipeline. State information of the system is sampled while any of the multiple selected instructions are in any stage of the pipeline. Software is informed whenever all of the selected instructions leave the pipeline so that the software can read any of the state information.