发明名称 Semiconductor memory device
摘要 Memory cell arrays, in which memory cells are arranged in a matrix, are divided into a plurality of blocks. In a semiconductor memory device having the memory cell arrays, load circuits are connected to bus lines and the memory cell arrays. The number of load circuits is the same as that of the memory cell arrays. Thus, the load circuits function to supply the same amount of current to the bus lines, whatever block is activated in a writing operation. Therefore, writing characteristics of all the memory cell array blocks are the same.
申请公布号 US5909406(A) 申请公布日期 1999.06.01
申请号 US19980030671 申请日期 1998.02.25
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 TAURA, TADAYUKI;ATSUMI, SHIGERU;UMEZAWA, AKIRA
分类号 H01L21/8247;G11C7/10;G11C11/4096;H01L27/10;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):G11C8/00;G11C7/00 主分类号 H01L21/8247
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