Word line multi-selection circuit for a memory device

摘要

A semiconductor memory device, such as a DRAM, includes a word line multi-selection circuit. A row decoder generates a word line selecting signal for selecting a read-out word line for use in the current cycle to read information from a selected memory cell. The word line selecting signal is also used to select a write-back word line which was used in the previous cycle to read cell information and is used in the current cycle to write back cell information. The word line multi-selection circuit includes a register for temporarily storing the cell information read from the selected memory cell and also for providing, in the current cycle, information read in the previous cycle in order to perform the write-back operation.