| 摘要 |
An analog-to digital converter (10) employs a capacitor circuit (12) for integra ting a sample of an input signal (20) during a predetermined interval of time and, thereafter, the capacitor (42) is discharg ed at a predetermined rate until the intergration voltage is equal to that of a reference. The discharge time serves as a measure of the amplitude of the input signal. A measurement interval is established which is equal to an integral number of cycles of each o f the possible values of frequency of the A.C. excitation. The signal integration interval has a duration less than or approxim ately equal to the shortest period of the A.C. exitation, this being the period of the highest frequency A.C. excitation. The signal inte gration is repeated periodically at each third half-cycle of the highest frequency excitation so that the total integration time experienc ed during positive half cycles is equal to that experienced during negative half cycles of any of the plurality of excitation fr equencies. This cancels the effect of noise due to signal polarity.
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