| 摘要 |
The present invention discloses a precharge circuit for preventing undesired output pulses caused by the current sensing circuit of the flash memory devices. The access time of the read-cycle also can be decreased after the undesired output pulses are completely removed. Basically, the circuit disclosed by the invention encompasses the current mirror and the cell array as conventionally; a control circuit, a voltage detector and a precharge circuit to remove the undesired output pulses. The control circuit couples with the current mirror, the voltage detector, and the precharge circuit. The current mirror is used to generate output waveform. The precharge circuit couples with the cell array with a bit line, and pre-charges the voltage level of the bit line to a predetermined expected value. The control circuit controls the precharge circuit to precharge the bit line when the read-cycle starts. Whole the current sensing circuit keeps disable until the voltage level of the bit line rises to an expected value. The output signal is then generated according to the logic-state of selected memory cell of the flash memory. The invalid logic 1 will never appear whatever the logic-state of the selected memory cell is.
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