| 摘要 |
PROBLEM TO BE SOLVED: To design so as to obtain a high operating frequency by reducing a margin, even in the case of generating timing signals used in an internal circuit by a delay device from clock signals. SOLUTION: A delay device 7 is constituted by cascade connection of plural stages of time constant circuits composed of an inverter and a series-connected circuit of a MOS transistor and a capacitor which is connected parallel to the output of the inverter. The ON resistance of the MOS transistor is changed by voltage control signals 107 of a voltage controlled oscillator 5. By controlling delay time by the inside delay device 7 from outside, delay time of the delay device for generating the timing signals of the internal circuit is changed, and by reducing a frequency, a normal operation is realized. |
