| 摘要 |
PROBLEM TO BE SOLVED: To make compatible a wide frequency variable range and high frequency stability at the time of fee run. SOLUTION: When a carrier asynchronous detection circuit 9 detects the out-of-synchronism in the carrier of input data, a '0' fixing circuit invalidates the phase error between a timing signal for generating the phase information of a regenerated clock signal synchronized with the input data and the regenerated clock signal, an integrator 3 generates the phase information of the regenerated clock signal to be increased for a fixed amount and based on the amplitude information of a sine waveform read out of a memory by the phase information, the regenerated clock signal asynchronous with the input data is generated with the high frequency stability in a fixed cycle regardless of the phase error. |
