发明名称 METHOD AND DEVICE FOR ANALYSIS OF SEMICONDUCTOR INTEGRATED CIRCUIT INSPECTION POINT
摘要 PROBLEM TO BE SOLVED: To decrease the overhead of a signal delay by the insertion of inspection points. SOLUTION: Discriminating of wheaten inspection point is insertable or net is performed and a circuit deformation method is calculated when inspection points are insertable for each signal line in the circuit from circuit information 122, an inspection point insertion library 123 whereby insertable types of inspection points and a circuit deformation method are designated, and inspection point insertion prohibited information 124 whereby a inspection point insertion prohibiting signal line and the set of inspection point types are designated. Next inspection point indexes for inspection point representatives into which inspection points are insertable are calculated and, based on the indexes thus obtained, those inspection representatives which can be easily tested are selected, and the selected results are recorded in the inspection point information 127. The processing above is repeated until the termination conditions of a preset inspection point analysis processing are satisfied.
申请公布号 JPH11142481(A) 申请公布日期 1999.05.28
申请号 JP19970311738 申请日期 1997.11.13
申请人 HITACHI LTD 发明人 NAKAO TAKANOBU;HATAKEYAMA KAZUMI;HIRANO JUN
分类号 G01R31/28;G06F11/22;G06F17/50 主分类号 G01R31/28
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