| 摘要 |
PROBLEM TO BE SOLVED: To provide a signature compressing circuit having a reduced masking probability by providing a first multi-input signature register(MISR) and a second MISR directly connected to the first MISR on the compressing circuit compressing the response data from an electronic circuit under inspection. SOLUTION: A parallel compressing circuit preventing the error masking by the repetitive error pattern of an odd distance is provided with two MISRs 42-1, 42-2. Six flip-flop(FF) circuits 43 corresponding to the inspection output patterns P1-P6 of the MISR 42-1 are connected to FF circuits on the superior gate side through XOR gates 47. The MISR 42-1 is provided with feedback taps. The output of a gate 45 is fed to a gate 44-1. The MISR 42-2 is provided with six FFs 46 corresponding to the outputs of the FF circuits 43. The FF circuits 43 are connected to corresponding next FF circuits on the superior bit side through the XOR gates 47. The output of a gate 48 is fed to the gate 44-1. |
