DEVICE FOR GENERATING A PLURALITY OF CODE SERIES SIMULTANEOUSLY AND CDMA RADIO RECEIVER COMPRISING THE DEVICE

摘要

The outputs of a plurality of shift stages (S1, S2 and S4) of an M-series generator (31A) are subjected to EOR (XR11 and XR12) and the output code of the generator (31A) is delayed by required bits, for example, 3 bits, to generate a 3-bit delay M-series. In a similar way, the outputs of a plurality of shift stages are combined and subjected to EOR to generate another delayed M-series. The outputs of simultaneous delayed code generators (31) and the output of another M-series generator (32) are subjected to EOR to generate a plurality of gold code series simultaneously.